The present invention relates to an information processing structure for processing information by means of an electronic structure of a nanometer (nm) scale, for example from 10 nm to 0.3 nm and in particular to an information processing structure for detecting similarity of one pattern to another by way of single electron operations.
The progress of microelectronics techniques for semiconductors in recent years has come to make it possible to manufacture a structure of the so-called nanometer (nm) scale, for example 10 nm or less. Utilizing such a microelectronics technique to fabricate a structure extremely small in electrostatic capacitance makes the so-called Coulomb blockade phenomenon observable that a single electron in the structure has its electrostatic energy so increased that no other electron can come into the structure. And it also makes movement of an individual electron controllable by Coulomb repulsion between them.
It is thus possible to make a small conductor (microconductor or small semiconductor (microsemiconductor)) domain in which an electron can be extant (hereinafter referred to as a xe2x80x9cquantum dotxe2x80x9d) by combining an energy barrier that the electron can directly tunnel (hereinafter referred to as a xe2x80x9ctunnel junctionxe2x80x9d) and a coupling with which the electron cannot directly tunnel the barrier hereinafter referred to as a xe2x80x9ccapacitive couplingxe2x80x9d), and then to form an electronic structure by combining such quantum dots. As is well known, such quantum dots can be formed by the self-assembling formation in which silicon quantum dots are formed by low pressure CVD using mono-silane (see Mat. Res. Soc. Symp. Proc. 452 (1997) 243 xe2x80x9cSelf-Assembling Formation of Silicon Quantum Dots by Low Pressure Chemical Vapor Depositionxe2x80x9d).
An electronic device when formed of such an electronic structure becomes to be operable by movement of a single electron. Such an electronic device is commonly called a single electron device, and a variety of single electron circuits have been proposed by taking advantage of single electron devices. For example, it is possible to form as an electronic device a complementary transistor akin to a CMOSFET, and a single electron logic circuit using such a complementary transistor has already been proposed (See J. Appl. Phys., Vol. 72, No. 9, 1992, pp. 4399-4413, J. R. Tucker: xe2x80x9cComplementary Digital Logic Based on the Coulomb Blockadexe2x80x9d).
Such proposals made for a single electron logic circuit, however, have so far not gone beyond only its circuit makeup by combining a tunnel junction and a capacitor on the circuit diagram level, and has scarcely as yet been implemented as a practical form, namely as an actual structure of the circuit.
Also, as regards a memory, while a xe2x80x9cquantum dot floating gate memory structurexe2x80x9d which it is designed to form by microstructuring the conventional floating gate structure has been proposed and made by way of trial, no practical form of implementation or no actual structure of the circuit has as yet been proposed that effectuates logics for information processing.
By the way, there is one important form of information processing operations that detects similarity of one pattern to another. This is a basic processing operation that can be utilized in a wide range of information processing including pattern recognition for associative memory, vector quantization and prediction of a movement and data compression.
In such processing operations, use may be made of a xe2x80x9cHamming distancexe2x80x9d as an index to indicate similarity between digital patterns. This is defined by the number of those bits differing from each other of the digital patterns. Thus, it follows that the smaller the difference in the number of such different bits, the smaller the Hamming distance and the higher the similarity between the patterns, viz. more closely the patterns resemble each other. Here, the Hamming distance can be computed, for example, by finding the exclusive ORs (XORs) of corresponding pairs of bits of the two digital patterns and summing those with the 1 output.
By the way, a circuit as shown in FIG. 14(A) having a capacitor C0 combined with a single electron transistor (hereinafter referred to as xe2x80x9cSETxe2x80x9d) made up of a pair of tunnel junctions 1 and 2 exhibits a non-monotone characteristic as presented by the aforementioned Coulomb blockade phenomenon (See Applied Physics [a Japanese journal], Vol. 66, No. 2(1997), p. 100) and therefore, if supplied with voltages Va and Vb via capacitors at an intermediate point between the two tunnel junction 1 and 2, namely at its isolated node 3, exhibits a change with time dependence of its output voltage Vco as shown in FIG. 14(B) depending on a combination in H or L level of the input voltages Va and Vb. Utilizing such a characteristic, there has been proposed a single electron logic circuit designed to provide an XNOR (exclusive NOR or inhibit exclusive OR) gate by combining a single SET with a capacitor C0 (See xe2x80x9cA Stochastic Associative Memory Using Single Electron Devices and Its Application to Digit Pattern Associationxe2x80x9d, T. Yamanaka et al, in Ext. Abs. of Int. Conf. on Solid State Devices and Materials, pp. 190-191, Hiroshima, September 1998).
FIG. 15 shows a further single electron logic circuit in which a pair of SETs is connected parallel to each other between a power supply Vdd and a capacitor C0 and to which inverted voltages of Va and Vb are also applied, thus providing a complementary structure. Such single electron logic circuits may be prepared in number equal to the number of bits of digital patterns to be compared with each other and may be connected to a common capacitor (C0) to make up a bit comparator (BC) for the digital patterns as shown in FIG. 16 in which Va represents a bit voltage of one digital pattern to be compared and Vb represents a bit voltage of the other digital pattern to compare with. Then in the SETs in which their respective bits coincide with each other (Va=Vb), the electron moves from the capacitor C0 to the power supply Vdd, raising the potential at the capacitor C0 as shown in FIG. 15(B). It follows therefore that the greater the number of bits coincident with each other, the more rapidly the capacitor potential Vc0 rises. Therefore, examining a transient change in the potential rise permits the size of the relative Hamming distance to be known. A bit comparator for digital patterns of such a construction has already been proposed.
Also, given the fact that a circuit formed of single electron devices operates stochastically, it has previously been known that conversely utilizing this stochastic nature makes it possible to realize an intelligent processing operation which it has been hard to realize in an existing CMOS circuit (See Yamanaka et al, 1998 supra; and IEICE Tramn. Electron., Vol. E81-C. No. 1, pp. 30-35, 1998, M. Saen et al, xe2x80x9cA Stochastic Associative Memory Using Single Electron Devicesxe2x80x9d).
No such single electron logic circuit has as yet been proposed, however, as to in what structure it may actually be implemented.
Also, the problem has existed that because as the time elapses the electric potential Vco of the capacitor C0 becomes constant without depending on the Hamming distance, the Hamming distance cannot be measured in a stable state.
Further, making a single electron logic circuit by applying the existing architecture of a CMOS logic circuit thereto involves theoretically fatal problems as mentioned below.
First, the fact that the tunneling phenomenon on the basis of which a single electron circuit operates is stochastic requires it to take fairly long before its operation is established, and makes the operation slow. Thus, the single electron logic circuit made by applying the architecture of a CMOS logic circuit must be slower in operation than, and hence fail to be superior to, the conventional CMOS logic circuit.
Second, no stable single electron operation can be obtained unless the electrostatic energy of one electron is enough larger than its thermal energy. This requires that an extremely small capacitance should be realized for a single electron logic circuit to be operated at a room temperature. Thus, in order for a very large scale integrated circuit with, say, 1010 gates to be operated without fail at the room temperature over 10 years, there must be realized a capacitance as very small as 10xe2x88x9220 Farad (see Jpn. J. Appl. Phys., Vol. 38, 1999, pp. 403-405, S. Shimano, K. Masu and K. Tsubouchi xe2x80x9cReliability of Single Electron Transistor Circuits Based on Eb/No-Bit Error Rate Characteristicsxe2x80x9d).
Consequently, providing such a small capacitance requires a structure of a size smaller than the atomic scale but in the actuality is impossible of realization.
Third, a charge tends to be trapped by an impurity and an interfacial energy level that unavoidably are present in the circumference of a dot, and the trapped charge gives rise to a charge in the dot, as it is called xe2x80x9coffset chargexe2x80x9d or xe2x80x9cbackground chargexe2x80x9d, thus presenting the problem that the single electron operation cannot be effected ideally.
With the foregoing points taken into account, the present invention is aimed to provide information processing structures formed of a plurality of single electron circuits each of which operates rapidly and stably by way of a single electron operation at a room temperature.
In order to achieve the object mentioned above, there is provided in accordance with the present invention, in a first construction thereof an information processing structure having a MOSFET, and a plurality of quantum dots disposed immediately above a gate electrode of the MOSFET and each of which is made of a microconductor or microsemiconductor of a nanometer scale in size, wherein there is formed between each of the quantum dots and the gate electrode an energy barrier that a charge carrier consisting of either an electron or positive hole is capable of directly tunneling, and the total number of such charge carriers moved between the quantum dots and the gate electrode is used to represent information, wherein the structure comprises: a power source electrode disposed in contact with the said quantum dots; and at least a pair of information electrodes disposed across the said quantum dot in contact therewith for having electric potentials applied thereto, representing data of information, wherein there is formed between each of the said quantum dots and the said power source electrode a potential barrier that a said charge carrier is capable of tunneling, a capacitive coupling is provided between each of the said information electrodes in each of the said pairs and a said quantum dot between them to prevent movement of a said charge carrier between the said quantum dot and each of the said information electrodes, and a said charge carrier is rendered movable by the Coulomb blockade through the said quantum dot between the said power source electrode and the said gate electrode in response to a relative electric potential determined at the said information electrodes.
The object mentioned above is also achieved in accordance with the present invention in a second construction thereof by an information processing structure having a MOSFET, and a plurality of quantum dots of a first group formed immediately above a gate electrode of the MOSFET and each of which is made of a microconductor or microsemiconductor of a nanometer scale in size, wherein there is formed between each of the quantum dots of the first group and the gate electrode an energy barrier that a charge carrier consisting of either an electron or positive hole is capable of directly tunneling, and the total number of such charge carriers moved between the quantum dots of the first group and the gate electrode is used to represent information, wherein the structure comprises: a plurality of lines of quantum dots of a second group each of which lines has at least three quantum dots of the second group arranged in contact with a said quantum dot of the first group associated therewith but not in contact with the said gate electrode; and a plurality of pairs of information electrodes, the said information electrodes in each pair being disposed in contact with those quantum dots of the second group which are formed at opposite ends of each of the said lines, respectively, for having electric potentials applied thereto, representing data of information, wherein a capacitive coupling is provided each between the said quantum dot of the first group and the said quantum dots of the second group in each of the said lines, and between the said quantum dots of the second group in each such line and each of the said information electrodes in each pair corresponding thereto to prevent movement of a said charge carrier each between them, and wherein a change caused in position distribution of a said charge carrier in the said quantum dots of the second group in each such line in response to a relative electric potential determined at the said information electrodes in the pair corresponding thereto makes a said charge carrier movable between the said quantum dot of the first group and the said gate electrode.
In a said information processing structure according to the present invention, the said quantum dots of the first group are preferably arranged in a plurality of lines of quantum dots of the first group.
In a said information processing structure according to the present invention, a said information electrode is preferably formed by at least one quantum dot of a third group, and the number of charge carriers as aforesaid stored on such quantum dots of the third group is used to represent information.
In a said information processing structure according to the present invention, preferably a second power source electrode is formed in contact with the information electrodes formed by the said quantum dots of the third group, there is formed between the said information electrode and the said second power source electrode an energy barrier that a said charge carrier is not capable of directly tunneling, and a voltage or light energy applied to the said energy barrier makes a said charge carrier movable between the said information electrode and the said second power source electrode.
The object mentioned above is also achieved in accordance with the present invention, in a third construction thereof by an information processing structure that comprises: a line of quantum dots each of which is made of a microconductor or microsemiconductor and in which line there is formed between adjacent quantum dots an energy barrier that a charge carrier is capable of directly tunneling; a pair of information electrodes disposed across the said line of quantum dots and in contact with those quantum dots which are located at opposite ends of the said line of quantum dots, respectively, wherein there is provided a capacitive coupling between each of the said information electrodes and the said quantum dot located in contact therewith to prevent movement of a charge carrier between them; and a power source electrode formed in contact with that quantum dot which is located at a center of the said line of quantum dots, wherein there is provided a capacitive coupling between the said power source electrode and the said central quantum dot to prevent movement of a charge carrier between them, wherein the said power source electrode is adapted to have a voltage applied thereto so that the said quantum dots in the line has a potential distribution such that a potential valley is formed about the said central quantum dot, and wherein a charge carrier placed on the said central quantum dot in the line is either immobile, or movable according to thermal fluctuation to one of the information electrode in the pair, depending upon a potential distribution determined by relative voltages at the said information electrodes.
According to an information processing structure of the first construction mentioned above, a plurality of single electron circuits each containing a plurality of quantum dots and a plurality of a pair of information electrode formed on the gate electrode of a MOSFET, and a power supply electrode thereof perform parallel information processing. With each of the single electron circuits taking out its processing result as a drain current on the MOSFET, the structure is capable of achieving a macroscopic information processing operation by putting together the processing results of these single electron circuits on the MOSFET. It can thus accomplish similarity computation for a multi-bit pattern on the single MOSFET.
Here, these single electron circuits permitting extremely low power consumption and a high degree of integration permits a super-parallel processing operation to be adopted to achieve a high processing speed.
Furthermore, parallel operations by a plurality of quantum dots make any strict operation unnecessary but a stochastic operation sufficient, which thus makes the structure operable even at a room temperature.
Furthermore, parallel operations by a plurality of quantum dots allows a redundancy configuration or majority logic to be utilized to control the influence of offset charges over the entire circuit system as much as practicable.
Also, as plural quantum dots may be supplied commonly with an identical input signal, the power source electrode and the information electrodes may be larger in size than the quantum dots and may thus be made up of a wiring pattern by the conventional lithographic method.
An information processing structure of the second construction mentioned above is not only operable well as of the first construction, but also has the advantage that it can quantify the similarity (in terms of Hamming distance) more clearly as the number of electrons in a stable state.
An information processing structure according to the third construction mentioned above has the advantage that it is operable in a wider temperature range and operable even at a room temperature.
If a second power source electrode is formed in contact with the information electrodes formed by the quantum dots such that there is formed between each information electrode and the second power source electrode an energy barrier that a charge carrier is not capable of directly tunneling, and a voltage or light energy applied to said energy barrier makes a charge carrier movable between the information electrode and the second power source electrode, it follows that the charge carrier is placed and held on the information electrode with the aid of the voltage or light energy, thus facilitating entry of data of information onto the information electrodes.